1. Field of the Invention
The present invention relates to a packet switch and, more particularly, to architectures and control methods for a switch wherein packets are pipelined in serial bits into and out of a one-stop packet buffer residing in a memory storage that allows massive parallel access.
2. Description of the Background Art
Buffer memory is commonly employed in packet switches to relieve the packet loss due to collisions of packets, e.g., packets bound for the same output within the same time interval. There have been different strategies in the deployment of the packet buffer memory to mitigate such occurrences, such as output buffering, crosspoint buffering, and input buffering. For discussion purposes below, it is convenient to visualize a representative format for a conventional packet as a data unit having overall fixed length (a specified number of bits or bytes) and being composed of a data payload preceded by a switching header. The switching header indicates the intended output address(es) as well as the QoS (Quality of Service) classification of the packet. In case the packet is merely an idle expression, both the switching header and the payload are, for example, strings of ‘0’ bits.
In particular, output buffering deploys a packet buffer associated with each output address, called an “output buffer”. Inside an output buffer is a packet queue. Normally in output-buffer switching architecture, each output buffer is allocated a separate block of the memory storage and the block is partitioned into a fixed number of registers, each for holding a packet. On the other hand, the length of the packet queue inside the buffer is dynamically changing. When all registers in the output buffer are occupied, further packets entering the buffer will be blocked. Blocking of one output buffer may occur even though other output buffers associated with other output addresses are not full.
The “shared-buffer-memory” style of switching architecture addresses this problem by allowing all packet queues (each corresponding to an output) to dynamically share a large pool of registers. This sharing necessitates the access of the memory storage by multiple sources, wherein a source here means an input port receiving input packets. The straightforward implementation of such multiple access to the memory storage is by a “bus” time-shared among sources, i.e., each input port transmits data at a different time slot; the time-division multiplexing of the incoming packets from input ports to the bus is performed by a packet multiplexer. Thus the transmission over the bus and the memory intake must be at the bit rate M times higher than the bit rate of a single input, where M is the number of inputs. They are normally in 16, 32, or 64 parallel bits, with each bit over a separate wire, because of the technological limitations on the bandwidth over a single wire. Concomitantly the packet multiplexer must also perform the serial-to-parallel conversion of the packet format. Symmetrically, at the output end, a packet demultiplexer demultiplexes packets from the shared buffer memory through another parallel-bit bus to output ports and performs the parallel-to-serial conversion of the packet format.
The throughput of a shared-buffer-memory switch is limited by the bandwidth of the memory bus, which is potentially also a single point of failure. Therefore, the shared-buffer-memory style of switching architecture does not scale well for large number of broadband I/O ports. A new architecture of a shared-buffer-memory switch that can scale well is a necessity for high-throughput applications. Meanwhile, it would be especially advantageous to save the cost in the memory-bus operations of multiplexing, demultiplexing, serial-to-parallel conversion, and parallel-to-serial conversion.
A “one-stop buffer” is a component known in the art which, in the context of a packet switch, means a packet buffer such that whenever a packet occupies a certain section, e.g., a register, in the buffer, it remains in that section until its eventual exit from the switch. One-stop buffering is desirable in packet switching because moving buffered packets around in real time is a costly operation as alluded to above. The subject matter of the present invention relates to a one-stop buffer.